Conventionally, semiconductor devices have benefited from lowering manufacturing cost, increasing operation speeds, lowering power consumption and increasing reliability from increasing integration in accordance with Moore's Law. However, when design rules become finer than 180 nanometers, referred to as SOC (System On Chip), the scale of a system which can be integrated onto a chip becomes extremely large.
To achieve even higher integration, there arises a demand for simultaneously integrating a large-scale memory circuit such as a DRAM or flash memory together with a high-speed analog circuit such as an RF.
However, to form these circuits on one chip, a wafer manufacturing process becomes extremely complicated and hence, the optimization of the manufacturing process for respective functions of mounted logic memory analog and the like becomes difficult. The integration of these circuits on one chip also gives rise to drawbacks such as the increase of leakage and substrate noise.
Further, although memory cells, logic cells and the like enjoy benefits by miniaturization of the semiconductor circuit, it is difficult to miniaturize an interface circuit, an analog circuit, a high breakdown resistance circuit and the like and hence, areas which these circuits occupy in the chip become non-uniform. Further, a cost for development including an expense for masks and a period for development are remarkably increased. These conditions are fatal to the semiconductor device also in view of the shortening of product lifetime in a market of final products.
In view of the above, particularly with respect to a system which performs an SOC in the wafer manufacturing process with a design rule exceeding 90 nanometers, an extremely high performance is requested and, at the same time, the system is limited to a system which is capable of realizing the mass production. To obviate such drawbacks, a technique which is referred to as a SIP (System In Package) which obviates the above-mentioned drawbacks by storing a plurality of semiconductor integrated circuit chips or different kinds of chips in one package is spreading. With the use of this technique, it is possible to make the semiconductor device have multi functions such as mixed mounting using chips made by different companies or mixed mounting of chips using different kinds of optical, mechanical chips or the like.
Such a conventional SIP technique is disclosed, for example, in patent document 1 or in patent document 2. In this conventional SIP, for example, two different semiconductor integrated circuit chips are laminated on a lead frame in a stacked manner. That is, the SIP is configured such that the semiconductor chip is mounted on the lead frame, and the semiconductor chip is mounted on a chip. Further, in the SIP, the chip is bonded to the lead frame from bonding pads by wires. Further, in the SIP, the chip is bonded to the lead frame from bonding pads by wires. By such a constitution, mounting of semiconductor integrated circuit chips with high packaging density can be realized.
Further, as another example of the conventional technique, there has been known a technique in which additional wiring lines are applied to a semiconductor integrated circuit chip such as a CSP (Chip Size Package) or a flip-chip and, thereafter, bumps made of solder, gold or copper are formed and compression-bonded to a substrate thus realizing the mounting of the highly packed semiconductor integrated circuit chip.
Patent document 1: JP-A-2004-134715
Patent document 2: JP-A-2003-007960
Disclosure Of The Invention
Problems to be solved by the Invention
However, in the conventional technique, when only wire bonding is used, wires are used in forming an internal bus which is not connected with an external portion. As a result, a large parasitic inductance and capacitance are added to the internal bus and hence, the use of the semiconductor device in high-speed applications is extremely difficult. Further, when the bumps are formed on the semiconductor integrated circuit chip after applying additional wiring lines to the semiconductor integrated circuit chip as in the case of the CSP or the flip-chip, additional step becomes necessary for respective chips and hence, a manufacturing cost is pushed up.
Accordingly, the present invention has been made to overcome the above-mentioned drawbacks and it is an object of the present invention to provide a semiconductor device which realizes the mounting of a plurality of chips with higher speeds, with higher packaging density and at a low cost than a conventional technique such as a SIP.
Means for solving the Problems
To achieve the above-mentioned object, a semiconductor device of the present invention includes: a wiring chip having a pair of first connection pad groups constituted by a plurality of wiring lines arranged in parallel and a plurality of pads connected to respective one end side and other end side of the wiring lines; a first semiconductor chip, having a group of second connection pads formed of a plurality of pads arranged along one side thereof, and a second semiconductor chip having a group of third connection pad which is formed of a plurality of pads arranged along one side thereof, wherein the first semiconductor chip and the second semiconductor chip are mounted on the wiring chip such that the one side along which the group of second connection pads of the first semiconductor chip are formed and the one side along which the group of third connection pads of the second semiconductor chip are formed to face each other, the group of first connection pads on one side and the group of second connection pads are connected with each other, and the group of first connection pads on another side and the group of third connection pads are connected with each other.
In the semiconductor device of the present invention, when the first semiconductor chip and the second semiconductor chip are mounted on the wiring chip, the arrangement positions of the respective groups of connection pads assume a shortest distance. Corresponding to such arrangement positions, wiring lines which are formed on the wiring chip become short. Accordingly, the first and second semiconductor chips can be mounted on the wiring chip with high packaging density and, at the same time, the wiring distance can be shortened to realize the high-speed operation.
Further, the wiring chip can use an extremely stable manufacturing process compared to the semiconductor chips which are mounted on the wiring chip. Further, the wiring chip can be constituted by merely providing the connection pads and the wiring layer for mounting the semiconductor chip and hence, a high yield can be realized. As a result, it is possible to suppress the increase of a cost of the wiring chip.
Further, since the cost of the wiring chip is lowered, it is possible to form passive elements such as resistors, capacitors, inductances and the like on the wiring chip.
In the present invention, at least one of the first semiconductor chip and the second semiconductor chip may be mounted on the wiring chip via bumps by flip-chip mounting. By mounting the respective semiconductor chips on the wiring chip by flip-chip mounting such that the respective connection bumps are bonded to (connected to) each other via the bumps, compared to a case in which the respective connection bumps are connected with bonding wires, for example, the inductance is reduced to approximately one tenth and hence, it is possible to realize a high-speed interface between internal signals.
Although the bumps are preliminarily formed on the respective pads of the either one or both groups of connection pads, particularly, the bumps may be preliminarily formed on the pads of the first group of connection pads of the wiring chip. Accordingly, the bumps may be formed collectively for multiple chips and hence, a cost for forming the bumps may be lowered, and it is possible to use the existing semiconductor chips with no modification without forming additional wiring lines or bumps on the semiconductor chip to be mounted.
The bumps may be made of metal which contains Au. With the use of such bumps, it is possible to obtain the favorable connection between the respective connection pads.
In the present invention, the first group of connection pads may be constituted of 2000 to 5000 pieces of connection pads. Further, in the present invention, an arrangement pitch of the first to third groups of connection pads may be 20 μm to 60 μm. These number and arrangement pitch of the connection pads are suitably set corresponding to a kind of the semiconductor chip to be mounted.
In the present invention, a semiconductor substrate which constitutes the wiring chip, a semiconductor substrate which constitutes the first semiconductor chip and a semiconductor substrate which constitutes the second semiconductor chip are made of the same material, in particular, of a silicon. By forming the respective chips using the substrate made of the same material, particularly the silicon, a physical strength with respect to heat, elongation and contraction can be increased thus ensuring the high reliability.
In the present invention, the first semiconductor chip may be formed of a memory device chip having a memory means for inputting and outputting signals in parallel for each predetermined number of bits, and the second semiconductor chip may be formed of a specific-use logic circuit chip for inputting and outputting signals in parallel for each predetermined number of bits with the memory device chip. By such a constitution, it is possible to realize the high-speed inputting and outputting of signals while realizing the high packaging density mounting of the memory device chip and of the specific-use logic circuit chip.
In the present invention, the wiring chip may include a plurality of power source lines which supply a predetermined power source voltage to the first semiconductor chip and the second semiconductor chip. By such a constitution, it is possible to reinforce the power source by preventing the lowering of a potential.
In the present invention, a conductive line which prevents crosstalk may be provided between wiring lines of the wiring chip. By such a constitution, even when the wiring lines are formed densely, it is possible to perform the favorable inputting and outputting of signals between the semiconductor chips while preventing crosstalk.
In the present invention, pads for test may be further provided. By such a constitution, even when the first to third connection pads may be arranged with high packaging density, it is possible to perform the inspection of the respective chips. Further, by providing the pads for tests to the memory device chip, with the use of the pads for tests at the time of performing a wafer test of the memory device, it is possible to measure the memory device chip by inputting or outputting test signals to the pads for tests at the time of performing the wafer test.
In the present invention, a first group of power source pads formed of a plurality of pads is formed in a region where the second group of connection pads of the first semiconductor chip is not formed, and all pads which are positioned closest to an outermost periphery of the first semiconductor chip out of the second group of connection pads and the first group of power source pads are set as dummy pads which are not electrically connected with the first group of connection pads, a second group of power source pads formed of a plurality of pads is formed in a region where the third group of connection pads of the second semiconductor chip is not formed, and all pads which are positioned closest to an outermost periphery of the second semiconductor chip out of the third group of connection pads and the second group of power source pads are set as dummy pads which are not electrically connected with the first group of connection pads. By forming all pads which are positioned closest to the outermost periphery of the semiconductor chip where the neighboring pads (or the bumps) are liable to be easily short-circuited as dummy pads, it is possible to surely prevent a connection defect between the chips.
In the present invention, the respective pads of the second group of connection pads of the first semiconductor chip and the respective pads of the third group of connection pads of the second semiconductor chip are connected with each other via the wiring lines so as to make wiring lengths of all of the plurality of wiring lines which is arranged on the wiring chip equal to each other. By such a constitution, resistances of all wiring lines which connect the connection pads of the first semiconductor chip and the connection pads of the second semiconductor chip become equal.
Effect Of The Invention
According to the semiconductor device of the present invention, it is possible to provide the semiconductor device which realizes the mounting of a plurality of chips at a high speed, with high packaging density and at a low cost.